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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7630 group is a single chip 8-bit microcomputer designed with CMOS silicon gate technology. Being equipped with a CAN (Controller Area Network) module circuit, the microcomputer is suited to drive automotive equipments. The CAN module complies with CAN specification version 2.0, part B and allows priority-based message management. In addition to the microcomputers simple instruction set, the ROM, RAM and I/O addresses are placed in the same memory map to enable easy programming. The built-in ROM is available as mask ROM or One Time PROM. For development purposes, emulator- and EPROM-type microcomputers are available as well.
z z z z z z z z z z z
FEATURES
z z z z
Basic machine-language instructions . . . . . . . . . . . . . . . . . . 71 Minimum instruction execution time (at 10 MHz oscillation frequency) . . . . . . . . . . . . . . . . . . 0.2 s Memory size ROM . . . . . . . . . . . . . . . . . 16252 bytes (M37630M4T-XXXFP) RAM . . . . . . . . . . . . . . . . . . . 512 bytes (M37630M4T-XXXFP) I/O ports Programmable I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 24 sources, 24 vectors Timers 16-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels 8-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels Serial I/Os Clock synchronous. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel CAN module (CAN specification version 2.0, part B) . . . . . . . . . . . 1 channel A-D converter . . . . . . . . . . . . . . . . . . . . . . . . 8-bits x 8 channels Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Clock Generating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Built-in with internal feedback resistor Power source voltage (at 10 MHz oscillation frequency). . . . . . . . . . . . . . . 4.0 to 5.5 V Power dissipation In high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) Operating temperature range. . . . . . . . . . . . . . . . . -40 to 85 C Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44QFP (44P6N-A)
APPLICATION
Automotive controls
PIN CONFIGURATION (TOP VIEW)
P15/CNTR1 P16/PWM P14/CNTR0 P12/INT1 P11/INT0 P07/AN7 P06/AN6 P05/AN5
25
P04/AN4
24
33
32
31
30
29
28
27
26
23
P03/AN3
P13/TX0
P17 P20/SIN P21/SOUT P22/SCLK P23/SRDY VSS P24/URXD P25/UTXD P26/URTS P27/UCTS P30
34 35 36 37 38 39 40 41 42 43 44
22 21 20 19
M37630M4T-XXXFP M37630E4T-XXXFP
18 17 16 15 14 13 12
P02/AN2 P01/AN1 P00/AN0 VREF AVSS VCC XOUT XIN VSS RESET P47/KW7
10
P34 P40/KW0
P41/KW1
P42/KW2
P43/KW3
P44/KW4
P45/KW5
Package type: 44P6N-A 44-pin plastic molded QFP
Fig. 1 Pin configuration of M37630M4T-XXXFP
P32/CRX
P46/KW6
P31/CTX
P33
11
1
2
3
4
5
6
7
8
9
1
Fig. 2
2
M37630MXT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE: 44P6N-A)
Clock output XOUT
16
Functional block diagram
Clock input XIN
15
Reset input RESET
13
VCC
17 14
VSS
39
AVSS
18
Clock generating circuit
CPU
A (8) X (8) Y (8) S (8)
ROM
RAM
WDT
2
Timer X (16) Timer Y (16)
Timer 1 (8) Timer 2 (8) Timer 3 (8) PWM
PCH (8)
PCL (8) PS (8)
key on wake up
CAN
2
UART
4
Serial I/O
4
A-D Converter
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INT0, INT1
2
8
MITSUBISHI MICROCOMPUTERS
P4 (8)
P3 (5)
P2 (8)
3
P1 (7)
P0 (8)
12 11 10 9 8 7 6 5
4 3 2 1 44
43 42 41 40 38 37 36 35
34 33 32 31 30 29 28
19
27 26 25 24 23 22 21 20
7630 Group
VREF input
I/O port P4
I/O port P3
I/O port P2
I/O port P1
I/O port P0
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1: Pin description Pin VCC, VSS AVSS Name Power source voltage Analog power source voltage Input/Output Description Power supply pins; apply 4.0 to 5.5 V to VCC and 0 V to VSS Ground pin for A-D converter. Connect to VSS Reset pin. This pin must be kept at "L" level for more than 2 s, to enter the reset state. If the crystal or ceramic resonator requires more time to stabilize, extend the "L" level period. Input and output pins of the internal clock generating circuit. Connect a ceramic or quartz-crystal resonator between the XIN and XOUT pins. When an external clock source is used, connect it to XIN and leave XOUT open. Reference voltage input pin for A-D converter
RESET
Reset input
Input
XIN XOUT VREF P00/AN0-- P07/AN7
Clock input Clock output Reference voltage input I/O port P0
Input Output Input
I/O
CMOS I/O ports or analog input ports CMOS input port or external interrupt input port. The active edge (rising or falling) of external interrupts can be selected. This pin will be used as VPP pin during PROM programming of One Time PROM Versions. CMOS I/O port or external interrupt input port. The active edge (rising or falling) of external interrupts can be selected. CMOS I/O port or input pin used in the bi-phase counter mode
P11/INT0
Input
P12/INT1 P13/TX0 P14/CNTR0 P15/CNTR1 P16/PWM P17 P20/SIN P21/SOUT P22/SCLK P23/SRDY I/O port P2 P24/URXD P25/UTXD P26/URTS P27/UCTS P30 P31/CTX I/O port P3 P32/CRX P33--P34 P40/KW0-- P47/KW7 I/O port P4 I/O I/O I/O I/O port P1 I/O
CMOS I/O port or timer X input pin used for the event counter, pulse width measurement and bi-phase counter mode CMOS I/O port or timer Y input pin used for the event counter, pulse width and pulse period measurement mode CMOS I/O port or PWM output pin used in the PWM mode of timers 2 and 3 CMOS I/O port
CMOS I/O ports or clock synchronous serial I/O pins
CMOS I/O ports or asynchronous serial I/O pins
CMOS I/O port CMOS I/O port or CAN transmit data pin CMOS I/O port or CAN receive data pin CMOS I/O port CMOS I/O ports. These ports can be used for key-on wake-up when configured as inputs.
3
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M37630
M
4
T-
XXX
FP Package type FP: 44P6N-A package FS: 80D0 package ROM number Omitted in One Time PROM version (blank) and EPROM version T: Automotive use ROM/PROM size 4: 16384 bytes The first 128 bytes and the last 4 bytes of ROM are reserved areas. They cannot be used. Memory type M: Mask ROM version E: EPROM or One Time PROM version
Fig. 3
Part numbering
4
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7630 group as follows:
Memory Size
ROM/PROM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes RAM size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 bytes
Memory Type
Support mask ROM, One Time PROM and EPROM versions.
Package
44P6N-A . . . . . . . . . . . . . . . . .0.8mm-pitch plastic molded QFP 80D0 . . . . . . . . . . . 0.8mm-pitch ceramic LCC (EPROM version)
ROM External 60K 48K 32K 28K 24K 20K M37630M4T 16K 12K 8K M37630E4T Mass product
Under development
384
512
640 RAM size (bytes)
768
896
1024
Fig. 4
Memory expansion plan
Currently supported products are listed below: Table 2: List of supported products Product M37630M4T-XXXFP M37630E4T-XXXFP M37630E4FP M37630E4FS 16384 (16252) 80D0 512 44P6N-A (P)ROM size (bytes) ROM size for User ( ) RAM size (bytes) Package Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Remarks As of March 1998
5
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The core of 7630 group microcomputers is the 7600 series CPU. This core is based on the standard instruction set of 740 series; however the performance is improved by allowing to execute the same instructions as that of the 740 series in less cycles. Refer to the 7600 Series Software Manual for details of the instruction set. 7 0 CPU mode register (address 000016) CPUM Processor mode bits (set these bits to "00") b1 b0 0 0: Single-chip mode 0 1: Not used 1 0: Not used 1 1: Not used Stack page selection bit 0 : 0 page 1 : 1 page Not used ("0" when read, do not write "1") Internal system clock selection bit 0 : =f(XIN) divided by 2 (high-speed mode) 1 : =f(XIN) divided by 8 (middle-speed mode) Not used ("0" when read, do not write "1")
CPU Mode Register CPUM
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated to address 000016.
Fig. 5
Structure of CPU mode register
6
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers.
Interrupt Vector Area
The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Zero Page
This area can be accessed most efficiently by means of the zero page addressing mode.
ROM
ROM is used for storing user's program code as well as the interrupt vector area. RAM area RAM size (byte) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX16 011F16 015F16 01DF16 025F16 02DF16 035F16 03DF16 045F16 06DF16 085F16
Special Page
This area can be accessed most efficiently by means of the special page addressing mode.
000016
004016
SFR area CAN SFRs Zero page
006016 00FF16
User RAM
XXXX16
086016
ROM area ROM size (byte) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
FFCA16 FFFB16 FFFC16 FFFF16 YYYY16 ZZZZ16
Not used
Reserved ROM area
ROM
FF0016
Interrupt vector area Reserved ROM area
Special page
Fig. 6
Memory map diagram
7
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SPECIAL FUNCTION REGISTERS (SFR)
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 CPU mode register Not used Interrupt request register A Interrupt request register B Interrupt request register C Interrupt control register A Interrupt control register B Interrupt control register C Port P0 register Port P0 direction register Port P1 register Port P1 direction register Port P2 register CPUM IREQA IREQB IREQC ICONA ICONB ICONC P0 P0D P1 P1D P2 P2D P3 P3D P4 P4D SIO SIOCON AD ADCON T1 T2 T3 T123M TXL TXH TYL TYH TXM TYM UMOD UBRG UCON USTS UTBR1 UTBR2 URBR1 URBR2 PUP0 PUP1 PUP2 PUP3 PUP4 IPOL WDT PCON 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 CAN transmit control register CAN bus timing control register 1 CAN bus timing control register 2 CAN acceptance code register 0 CAN acceptance code register 1 CAN acceptance code register 2 CAN acceptance code register 3 CAN acceptance code register 4 CAN acceptance mask register 0 CAN acceptance mask register 1 CAN acceptance mask register 2 CAN acceptance mask register 3 CAN acceptance mask register 4 CTRM CBTCON1 CBTCON2 CAC0 CAC1 CAC2 CAC3 CAC4 CAM0 CAM1 CAM2 CAM3 CAM4 CREC CABORT CTB0 CTB1 CTB2 CTB3 CTB4 CTB5 CTB6 CTB7 CTB8 CTB9 CTBA CTBB CTBC CTBD
Port P2 direction register 000E16 Port P3 register 000F16 Port P3 direction register 001016 Port P4 register 001116 Port P4 direction register 001216 Serial I/O shift register 001316 Serial I/O control register 001416 A-D conversion register 001516 A-D control register 001616 Timer 1 001716 Timer 2 001816 Timer 3 001916 Timer 123 mode register Timer XL Timer XH Timer YL Timer YH Timer X mode register Timer Y mode register UART mode register UART baud rate generator UART control register UART status register UART transmit buffer register 1 UART transmit buffer register 2 UART receive buffer register 1 UART receive buffer register 2 Port P0 pull-up control register Port P1 pull-up control register Port P2 pull-up control register Port P3 pull-up control register Port P4 pull-up/down control register Interrupt polarity selection register Watchdog timer register Polarity control register
CAN receive control register 003E16 CAN transmit abort register 003F16 Reserved 004016 CAN transmit buffer register 0 004116 CAN transmit buffer register 1 004216 CAN transmit buffer register 2 004316 CAN transmit buffer register 3 004416 CAN transmit buffer register 4 004516 CAN transmit buffer register 5 004616 CAN transmit buffer register 6 004716 CAN transmit buffer register 7 004816 CAN transmit buffer register 8 004916 CAN transmit buffer register 9 CAN transmit buffer register A CAN transmit buffer register B CAN transmit buffer register C CAN transmit buffer register D Reserved Reserved CAN receive buffer register 0 CAN receive buffer register 1 CAN receive buffer register 2 CAN receive buffer register 3 CAN receive buffer register 4 CAN receive buffer register 5 CAN receive buffer register 6 CAN receive buffer register 7 CAN receive buffer register 8 CAN receive buffer register 9 CAN receive buffer register A CAN receive buffer register B CAN receive buffer register C CAN receive buffer register D Reserved Reserved
001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16
004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
CRB0 CRB1 CRB2 CRB3 CRB4 CRB5 CRB6 CRB7 CRB8 CRB9 CRBA CRBB CRBC CRBD
Fig. 7
Memory map of special register (SFR)
8
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The 7630 group has 35 programmable I/O pins and one input pin arranged in five I/O ports (ports P0 to P4). The I/O ports are controlled by the corresponding port registers and port direction registers; each I/O pin can be controlled separately. When data is read from a port configured as an output port, the port latch's contents are read instead of the port level. A port configured 7 0 Port Pi register (i = 0 to 4) (address 000816 + 2 * i) Pi Port Pij control bit (j = 0 to 7) 0 : "L" level 1 : "H" level
Note : The control bits corresponding to P10, P35, P36 and P37 are not used ("0" when read, do not write "1").
as an input port becomes floating and its level can be read. Data written to this port will affect the port latch only; the port remains floating. Refer to Structure of port- and port direction registers, Structure of port I/Os (1) and Structure of port I/Os (2).
7
0 Port Pi direction register (i = 0 to 4) (address 000916 + 2 * i) PiD Port Pij direction control bit (j = 0 to 7) 0 : Port configured as input 1 : Port configured as output
Note : The direction control bits corresponding to P10, P11, P35, P36 and P37 are not used ("0" when read, do not write "1"). Port direction registers are undefined when read (write only).
Fig. 8
Structure of port- and port direction registers
9
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P00/AN0 to P07/AN7
Pull-up control bit Analog input selection Direction register Data bus Port latch
(4) Port P13/TX0
Pull-up control bit direction register Data bus Port latch
ADC input Analog input selection
Timer bi-phase mode input
(5) Ports P14/CNTR0, P15/CNTR1
Pull-up control bit
(2) Port P11/INT0
Interrupt input Data bus Data bus
Direction register Port latch
Timer bi-phase mode input
(3) Port P12/INT1
Pull-up control bit Direction register Data bus Port latch
(6) Port P16/PWM
Pull-up control bit PWM output enable Direction register Data bus Port latch
Interrupt input
PWM output
Fig. 9
Structure of port I/Os (1)
10
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Ports P17, P30, P33, P34
Pull-up control bit Direction register Data bus Port latch
(12) Ports P24/URXD, P27/UCTS
Transmission or reception* in Pull-up control bit progress Transmit or receive* enable bit Direction register Data bus Port latch
URXD or UCTS input
(8) Port P20/SIN
Pull-up control bit SIO Port Select Direction register Data bus Port latch
(13) Ports P25/UTXD, P26/URTS
Transmission or reception** in progress Transmit or receive** enable bit Direction register Data bus Port latch Pull-up control bit
SIO1 input
UTXD or URTS output
(*) for UCTS (**) for URTS
(9) Port P21/SOUT
Pull-up control bit SIO port selection bit Transmit complete signal Direction register Data bus Port latch
(14) Port P31/CTX
Pull-up control bit CAN port selection bit Direction register Data bus Port latch
SIO output
CTX output
(15) Port P32/CRX (10) Port P22/SCLK
Pull-up control bit Clock selection bit Port selection bit direction register Data bus Port latch CAN interrupt SIO clock output External clock input CRX input
CAN dominant level control bit Pull-up/down control bit
Direction register Data bus Port latch
(16) Ports P40/KW0 to P47/KW7 (11) Port P23/SRDY
Pull-up control bit SRDY output selection bit Direction register Data bus Port latch Key-on wake-up interrupt SRDY output Data bus
Key-on wake-up control bit Pull-up/down control bit
Direction register Port latch
Fig. 10
Structure of port I/Os (2)
11
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port Pull-up/pull-down Function
Each pin of ports P0 to P4 except P11 is equipped with a programmable pull-up transistor. P32/CRX and P40/KW0 to P47/KW7 are equipped with programmable pull-down transistors as well. The pull-up function of P0 to P3 can be controlled by the corresponding
port pull-up control registers (see Structure of port pull-up/down control registers). The pull-up/down function of ports P3 2 and P4 can be controlled by the corresponding port pull-up/pull-down registers together with the polarity control register (see Structure of polarity control register).
7
0 Port Pi pull-up control register (address 002816 + i) (i = 0, 2) PUP0, PUP2 Pij pull-up transistor control bit (j = 0 to 7) 0 : Pull-up transistor disabled 1 : Pull-up transistor enabled
7
0 Port P1 pull-up control register (address 002916) PUP1 Not used ("0" when read, do not write "1") P1j pull-up transistor control bit (j = 2 to 7)
7
0 Port P3 pull-up control register (address 002B16) PUP3 P3j pull-up transistor control bit (j = 0, 1) P32 pull-up/down transistor control bit P3j pull-up transistor control bit (j = 3, 4) Not used ("0" when read, do not write "1")
7
0 Port P4 pull-up/down control register (address 002C16) PUP4 P4j pull-up/down transistor control bit (j = 0 to 7)
0 : Pull-up/down transistor disabled 1 : Pull-up/down transistor enabled Fig. 11 7 Structure of port pull-up/down control registers 0 Polarity control register (address 002F16) PCON Key-on wake-up polarity control bit 0 : Low level active 1 : High level active CAN module dominant level control bit 0 : Low level dominant 1 : High level dominant Not used (undefined when read)
Fig. 12
Structure of polarity control register
12
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port Overvoltage Application
When configured as input ports, P1 to P4 may be subjected to overvoltage (VI > VCC) if the input current to the applicable port is limited to the specified values (see "Table 8:"). Use a serial resistor of appropriate size to limit the input current. To estimate the resistor value, assume the port voltage to be VCC at overvoltage condition. Notes: * Subjecting ports to overvoltage may effect the supply voltage. Assure to keep VCC and VSS within the target limits.
* *
Avoid to subject ports to overvoltage causing VCC to rise above 5.5 V. The overvoltage condition causing input current flowing through the internal port protection circuits has a negative effect on the ports noise immunity. Therefore, careful and intense testing of the target system's noise immunity is required. Refer to the "countermeasures against noise" of the corresponding users manual. Port P0 must not be subjected to overvoltage conditions.
*
13
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
There are 24 interrupts: 6 external, 17 internal, and 1 software. 2. 3.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs when the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be cleared or set by software. Interrupt request bits can be cleared by software but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupt requests occur at the same time, the interrupt with the highest priority is accepted first.
4.
The contents of the program counter and processor status register are automatically pushed onto the stack. Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program counter. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.
Notes on use
When the active edge of an external interrupt (INT0, INT1, CNTR0, CNTR1, CWKU or KOI) is changed, the corresponding interrupt request bit may also be set. Therefore, take the following sequence. (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register. (in the case of CNTR0: Timer X mode register; in the case of CNTR1: Timer Y mode register) (3) Clear the interrupt request bit to "0". (4) Enable the external interrupt which is selected.
Interrupt Operation
Upon acceptance of an interrupt, the following operations are automatically performed. 1. The processing being executed is stopped.
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MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
. Table 3: Interrupt vector addresses and priority Vector Address (Note 1) Interrupt source Reset (Note 2) Watchdog timer INT0 INT1 CAN successful
transmit
Priority High 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFDB16 FFD916 FFD716 FFD516 FFD316 Low FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 FFDA16 FFD816 FFD616 FFD416 FFD216
Interrupt Request Generating Conditions At Reset At Watchdog timer underflow At detection of either rising or falling edge of INT0 interrupt At detection of either rising or falling edge of INT1 interrupt At CAN module successful transmission of message At CAN module successful reception of message If CAN module receives message when receive buffers are full. When CAN module enters into error passive state When CAN module enters into bus off state When CAN module wakes up via CAN bus At Timer X underflow or overflow At Timer Y underflow At Timer 1 underflow At Timer 2 underflow At Timer 3 underflow At detection of either rising or falling edge in CNTR0 input At detection of either rising or falling edge in CNTR1 input At completion of UART receive At completion of UART transmit At UART transmit buffer empty When UART reception error occurs. At completion of serial I/O data transmit and receive At completion of A-D conversion At detection of either rising or falling edge of P4 input At BRK instruction execution
Remarks Non-maskable Non-maskable External Interrupt (active edge selectable) External Interrupt (active edge selectable) Valid when CAN module is activated and request transmit Valid when CAN module is activated Valid when CAN module is activated Valid when CAN module is active Valid when CAN module is active
CAN successful receive CAN overrun CAN error passive CAN error bus off CAN wake up Timer X Timer Y Timer 1 Timer 2 Timer 3 CNTR0 CNTR1 UART receive UART transmit UART transmit buffer empty UART receive error Serial I/O A-D conversion Key-on wake-up BRK instruction
External Interrupt (active edge selectable) External Interrupt (active edge selectable) Valid when UART is selected Valid when UART is selected Valid when UART is selected Valid when UART is selected Valid when serial I/O is selected
22 23 24 25
FFD116 FFCF16 FFCD16 FFCB16
FFD016 FFCE16 FFCC16 FFCA16
External Interrupt (active edge selectable) Non-maskable
Notes 1: Vector addresses contain interrupt jump destination address 2: Reset function in the same way as an interrupt with the highest priority
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MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag I BRK instruction Reset Interrupt request
Fig. 13
Interrupt control
For the external interrupts INT0 and INT1, the active edge causing the interrupt request can be selected by the INT0 and INT1 interrupt edge selection bits of the interrupt polarity selection register (IPOL); please refer to Fig. 14 below.
7
0 Interrupt polarity selection register (Address 002D16) IPOL Not used (returns to "0" when read, do not write "1" in this bit) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (returns to "0" when read, do not write "1" in these bits) 0 : Falling edge active 1 : Rising edge active
Fig. 14
Structure of interrupt polarity selection register
16
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0
Interrupt request register A (address 000216) IREQA Not used (returns to "0" when read) External interrupt INT0 request bit External interrupt INT1 request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit
7
0
Interrupt control register A (address 000516) ICONA Not used (returns to "0" when read) External interrupt INT0 enable bit External interrupt INT1 enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit
7
0
Interrupt request register B (address 000316) IREQB CAN wake up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit
7
0 Interrupt control register B (address 000616) ICONB CAN wake-up interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit
7
0
Interrupt request register C (address 000416) IREQC UART receive complete (receive buffer full) interrupt request bit UART transmit complete (transmit register empty) interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I/O interrupt request bit AD conversion complete interrupt request bit Key-on wake-up interrupt request bit Not used (returns to "0" when read)
7
0
Interrupt control register C (address 000716) ICONC UART receive complete (receive buffer full) interrupt enable bit UART transmit complete (transmit register empty) interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive error interrupt enable bit Serial I/O interrupt enable bit AD conversion complete interrupt enable bit Key-on wake-up interrupt enable bit Not used (returns to "0" when read)
0 : No interrupt request 1 : Interrupt requested Fig. 15 Structure of interrupt request and control registers A, B and C
0: 1:
Interrupt disabled Interrupt enabled
17
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
KEY-ON WAKE-UP
"Key-on wake-up" is one way of returning from a power-down state caused by the STP or WIT instruction. Any terminal of port P4 can be used to generate the key-on wake-up interrupt request. The active polarity can be selected by the key-on wake-up polarity control bit of PCON (see Fig. 12). If any pin of port P4 has the selected active level applied, the key-on wake-up interrupt request will be set to "1". Please refer to Fig. 16.
key-on wake-up control bit P4Dj PUP4j
port P4j/KWj
...
key-on wake-up interrupt
port P4j I/O circuit j = 0 to 7
Fig. 16
Block diagram of key-on wake-up circuit
18
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 7630 group has five timers: two 16-bit timers and three 8-bit timers . All these timers will be described in detail below.
16-bit Timers
Timers X and Y are 16-bit timers with multiple operating modes. Please refer to Fig. 17.
1/4 1/16 1/64 1/128
TYM1,0 "00" "01" "10" "11" TXM5,4 "00", "11" "01" "10" count direction control TXM7 TXL latch (8) TXH latch (8)
TXL counter (8)
TXH counter (8)
TX interrupt request
P13/TX0 edge detector sign generator P14/CNTR0 edge detector "0" "1" "01"
down "00", "10", "11" TXM5, 4
CNTR0 interrupt request TXM6
1/2 1/8 1/32
"00" "01" "10"
TXM5, 4="11" TYM3, 2 "0x", "11" TYM7 TYM5, 4
TYL latch (8)
TYH latch (8)
TYL counter (8) "10" TYM5, 4="11" rising edge detector falling edge detector
TYH counter (8)
TY interrupt request
1/64 "11"
P15/CNTR1 "1"
"0"
TYM5, 4="01" "0x", "10"
"11" CNTR1 interrupt request TYM5, 4
TYM6
Fig. 17
Block diagram of timers X and Y ( is internal system clock) same address as TXL. Next, write the high-order byte. When this is finished, the data is placed in the timer X high-order reload latch and the low-order byte is transferred from its temporary register to the timer X low-order reload latch. Depending on the timer X write control bit, the latch contents are reloaded to the timer immediately (write control bit = "0") or on the next timer underflow (write control bit = "1"). Read method When reading the timer X, read the high-order byte first. This causes the timer X high- and low-order bytes to be transferred to temporary registers being assigned to the same addresses as TXH and TXL. Next, read the low-order byte which is read from the temporary register. This method assures the correct timer value can be read during the timer count operation. Timer X count stop control Regardless of the actual operating mode, timer X can be stopped by setting the timer X count stop bit (bit 7 of the timer X mode register) to "1".
Timer X
Timer X is a 16-bit timer with a 16-bit reload latch supporting the following operating modes: (1) Timer mode (2) Bi-phase counter mode (3) Event counter mode (4) Pulse width measurement mode These modes can be selected by the timer X mode register (TXM). In the timer- and pulse width measurement mode, the timer's count source can be selected by the timer X count source selection bits of the timer Y mode register (TYM). Please refer to the Figures below for the TXM and TYM bit assignment. On read or write access to timer X, note that the high-order and loworder bytes must be accessed in the specific order. Write method When writing to the timer X, write the low-order byte first. The data written is stored in a temporary register which is assigned to the
19
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 Timer X mode register (address 001E16) TXM Timer X data write control bit 0 : Data is written to latch and timer 1 : Data is written to latch only Not used ("0" when read, do not write "1") Timer X mode bits b5 b4 0 0: Timer mode 0 1: Bi-phase counter mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 polarity selection bit 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse width measurement mode, measure "H" period 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse width measurement mode, measure "L" period Timer X stop control bit 0 : Timer counting 1 : Timer stopped
Fig. 18
Structure of Timer X mode register address as TYL. Next, write the high-order byte. When this is finished, the data is placed in the timer Y high-order reload latch and the low-order byte is transferred from its temporary register to the timer Y low-order reload latch. Read method When reading the timer Y, read the high-order byte first. This causes the timer Y high- and low-order bytes to be transferred to temporary registers being assigned to the same addresses as TYH and TYL. Next, read the low-order byte which is read from the temporary register. This method assures the correct timer value can be read during timer count operation. Timer Y count stop control Regardless of the actual operating mode, timer Y can be stopped by setting the timer Y count stop bit (bit 7 of the timer Y mode register) to "1".
Timer Y
Timer Y is a 16 bit timer with a 16-bit reload latch supporting the following operating modes: (1) Timer mode (3) Event counter mode (5) Pulse period measurement mode (6) H/L pulse width measurement mode These modes can be selected by the timer Y mode register (TYM). In the timer, pulse period- and pulse width measurement modes' the timer's count source can be selected by the timer Y count source selection bits. Please refer to Fig. 19. On read or write access to timer Y, note that the high-order and loworder bytes must be accessed in a specific order. Write method When writing to timer Y, write the low-order byte first. The data written is stored in a temporary register which is assigned to the same
20
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 Timer Y mode register (address 001F16) TYM Timer X count source selection bits b1 b0 0 0: divided by 4 0 1: divided by 16 1 0: divided by 64 1 1: divided by 128 Timer Y count source selection bits b3 b2 0 0: divided by 2 0 1: divided by 8 1 0: divided by 32 1 1: divided by 64 Timer Y operation mode bits b5 b4 0 0: Timer mode 0 1: Pulse period measurement mode 1 0: Event counter mode 1 1: H/L pulse width measurement mode CNTR1 polarity selection bit 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse period measurement mode, refer to falling edges 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse period measurement mode, refer to rising edges Timer Y stop control bit 0 : Timer counting 1 : Timer stopped
Fig. 19
Structure of timer Y mode register ( is internal system clock) The count direction is determined by the edge polarity and level of count source inputs and may change during the count operation. Refer to the table below. Table 4: Timer X count direction in Bi-phase counter mode P13/TX0 Edge Edge L H L H P14/CNTR0 L H L H Edge Edge Count direction Up Down Down Up Down Up Up Down
Operating Modes
(1) Timer mode
This mode is available with timer X and timer Y. * Count source The count source for timer X and Y is the output of the corresponding clock divider. The division ratio can be selected by the timer Y mode register. * Operation Both timers X and Y are down counters. On a timer underflow, the corresponding timer interrupt request bit will be set to "1", the contents of the corresponding timer latches will be reloaded to the counters and counting continues.
(2) Bi-phase counter mode (quadruplicate)
This mode is available with timer X only. * Count source The count sources are P14/CNTR0 and the P13/TX0 pins. * Operation Timer X will count both rising and falling edges on both input pins (see above). Refer to Timer X bi-phase counter mode operation for the timing chart of the bi-phase counter mode.
On a timer over- or underflow, the corresponding interrupt request bit will be set to "1" and counting continues.
21
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P13/TX0 input signal
P14/CNTR0 input signal
TX counter
count direction
down
up
Fig. 20
Timer X bi-phase counter mode operation * Operation The active edge of input signal to be measured can be selected by CNTR1 polarity selection bit (Fig. 18). When this bit is set to "0", the time between two consecutive falling edges of the signal input to P15/CNTR1 pin will be measured, when the polarity bit is set to "1", the time between two consecutive rising edges will be measured. The timer counts down. On detection of an active edge of input signal, the contents of the TY counters will be transferred to temporary registers assigned to the same addresses as TY. At the same time, the contents of TY latches will be reloaded to the counters and counting continues. The active edge of input signal also causes the CNTR1 interrupt request bit to be set to "1". The measurement result may be obtained by reading timer Y during interrupt service.
(3) Event counter mode
This mode is available with timer X and timer Y. * Count source The count source for timer X is the input signal to the P14/CNTR0 pin and for timer Y the input signal to P15/CNTR1 pin. * Operation The timer counts down. On a timer underflow, the corresponding timer interrupt request bit will be set to "1", the contents of the corresponding timer latches will be reloaded to the counters and counting continues. The active edge used for counting can be selected by the polarity selection bit of the corresponding pin P14/CNTR0 or P15/CNTR1. These bits are part of TXM (Structure of Timer X mode register) and TYM (Structure of timer Y mode register (f is internal system clock)) registers.
(4) Pulse width measurement mode
This mode is available with timer X only. * Count source The count source is the output of timer X clock divider. The division ratio can be selected by the timer Y mode register. * Operation The timer counts down while the input signal level on P14/CNTR0 matches the active polarity selected by the CNTR0 polarity selection bit of TXM (Structure of Timer X mode register). On a timer underflow, the timer X interrupt request bit will be set to "1", the contents of the timer latches are reloaded to the counters and counting continues. When the input level changes from active polarity (as selected), the CNTR0 interrupt request bit will be set to "1." The measurement result may be obtained by reading timer X during interrupt service.
(6) H/L pulse width measurement mode
This mode is available with timer Y only. * * Count source The count source is the output of the timer Y's clock divider. Operation This mode measures both the "H" and "L" periods of a signal input to P15/CNTR1 pin continuously. On detection of any edge (rising or falling) of input signal to P15/CNTR1 pin, the contents of timer Y counters are stored to temporary registers which are assigned to the same addresses as timer Y. At the same time, the contents of timer Y latches are reloaded to the counters and counting continues. The detection of an edge causes the CNTR1 interrupt request bit to be set to "1" as well. The result of measurement may be obtained by reading timer Y during interrupt service. This read access will address the temporary registers. On a timer underflow, the timer Y interrupt request bit will be set to "1", the contents of timer Y latches will be transferred to the counters and counting continues.
(5) Pulse period measurement mode
This mode is available with timer Y only. * Count source The count source is the output of timer Y clock divider.
22
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER 1, TIMER 2, TIMER 3
Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one common pre-divider. Timer 1 can operate in the timer mode only,
1 1/8 1/32 1/128 T123M67
whereas timers 2 and 3 can be used to generate a PWM output signal timing as well. Timers 1 to 3 are down count timers. See Fig. 21.
"00" "01" "10" "11"
T1 latch (8)
T1 counter (8)
T1 interrupt
T2 latch (8) "1" "0" T2 counter (8) "0" "1"
T123M1
T123M3
T2 interrupt S Q R
T3 latch (8) "1"
T123M4
"0" T3 counter (8) "0" "1"
T123M1
T3 interrupt S Q R T123M0 S T Q
P1D6 T123M1 P16 latch
P16/PWM
Fig. 21
Block diagram of timers 1 to 3 ( is internal system clock) be selected by the timer count source selection bits of timer 123 mode register (T123M). Writing to timer 2 register affects the reload latch only or both of the reload latch and counter depending on the timer 2 write control bit of T123M. When the timer write control bit is set to "0", both latch and counter will be initialized simultaneously; when set to "1" only the reload latch will be initialized, on an underflow, the counter will be set to the modified reload value. Writing to timer 3 initializes latch and counter both. Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit to be set to "1".
Timer 1
The count source of timer 1 is the output of timer 123 pre-divider. The division ratio of the pre-divider can be selected by the predivider division ratio bits of timer 123 mode register (T123M). Refer to Timer 123 mode register configuration (f is internal system clock). On a timer 1 underflow, the timer 1 interrupt request bit will be set to "1". Writing to timer 1 initializes the latch and counter.
Timers 2 and 3
The count source of timers 2 and 3 can be either the output of the timer 123 pre-divider or the timer 1 underflow. The count source can
23
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 Timer 123 mode register (address 001916) T123M PWM polarity selection bit 0 : Start on "H" level output 1 : Start on "L" level output PWM output enable bit 0 : PWM output disabled 1 : PWM output enabled Timer 2 write control bit 0 : Latch and counter 1 : Latch only Timer 2 count source selection bit 0 : Timer 1 underflow 1 : Pre-divider output Timer 3 count source selection bit 0 : Timer 1 underflow 1 : Pre-divider output Not used ("0" when read, do not write "1") Pre-divider division ratio bits b7 b6 0 0: divided by 1 0 1: divided by 8 1 0: divided by 32 1 1: divided by 128
Fig. 22
Timer 123 mode register configuration ( is internal system clock)
Operating Modes (1) Timer Mode
This mode is available with timers 1 to 3. * Count source For timer 1, the count source is the output of the corresponding pre-divider. For timers 2 and 3, the count source can be separately selected to be either the pre-divider output or timer 1 underflow. Operation The timer counts down. On a timer underflow, the corresponding timer interrupt request bit will be set to "1", the contents of the corresponding timer latch will be reloaded to the counter and counting continues.
(2) PWM Mode
This mode is available with timer 2 and 3. * Count source The count source can be separately selected to be either the pre-divider output or timer 1 underflow. * Operation When the PWM-mode is enabled, timer 2 starts counting. As soon as timer 2 underflows, timer 2 stops and timer 3 starts counting. If bit 0 is set, timer 2 determines the low duration and the initial output level is low. Timer 3 determines the high duration. If bit 0 is zero timer 2 determines the high duration and the initial output level is high. In this case timer 3 determines the low duration. Note: Be sure to configure the P16/PWM pin as an output port before using PWM mode.
*
24
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/Os
The serial I/O section of 7630 group consists of one clock synchronous and one asynchronous (UART) interface. speeds. Refer to Block diagram of clock synchronous I/O (f is internal system clock). The operation of the clock synchronous serial I/O can be configured by the serial I/O control register SIOCON; refer to Fig. 25.
Clock Synchronous Serial I/O (SI/O)
The clock synchronous interface allows full duplex communication based on 8 bit word length. The transfer clock can be selected from an internal or external clock. When an internal clock is selected, a programmable clock divider allows eight different transmission
SIOCON2, 1, 0 Clock divider
P23/SRDY
SIOCON4 "1" "0" P23 latch Sync. circuit
SIOCON6 "1" "0"
P22/SCLK
SIOCON3 "1" "0" P22 latch SIO counter (3) SIO interrupt
P21/SOUT
SIOCON3 "1" "0" P21 latch SIO shift register (8)
P20/SIN
SIOCON3 "1" "0" P20 latch
Fig. 23
Block diagram of clock synchronous I/O ( is internal system clock) 001216). After an 8-bit transmission has been completed, the SOUT pin will change to high impedance and the SIO interrupt request bit will be set to "1". When an external transfer clock is selected, the SIO interrupt request bit will be set to "1" after 8 cycles but the contents of the SI/O shift register continue to be shifted while the transfer clock is being input. Therefore, the clock needs to be controlled externally; the SOUT pin will not change to high impedance automatically.
(1) Clock synchronous serial I/O operation
Either an internal or external transfer clock can be selected by bit 6 of SIOCON. The internal clock divider can be programmed by bits 0 to 2 of SIOCON. Bit 3 of SIOCON determines whether the double function pins P20 to P22 will act as I/O ports or serve as SIO pins. Bit 4 of SIOCON allows the same selection for pin P23. When an internal transfer clock is selected, transmission can be triggered by writing data to the SI/O shift register (SIO, address
25
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
synchronous clock transfer clock
write signal to SIO receive enable signal SRDY Serial Output SOUT Serial input SIN D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
SIO interrupt request bit = "1" Note: When an internal clock is selected, SOUT pin will change to high impedance after 8 bits of data have been transmitted.
Fig. 24
Timing of clock synchronous SI/O function (LSB first selected)
7
0 SIO control register (address 001316) SIOCON Clock divider selection bits
b2 b1 b0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0: 1: 0: 1: 0: 1: 0: 1:
divided by 4 divided by 8 divided by 16 divided by 32 divided by 64 divided by 128 divided by 256 divided by 512
P20/SIN, P21/SOUT and P22/SCLK function selection bit 0 : I/O port function 1 : SI/O function P23/SRDY function selection bit 0 : I/O port function 1 : SI/O function Transmission order selection bit 0 : LSB first 1 : MSB first Synchronization clock selection bit 0 : use external clock 1 : use internal clock Not used ("0" when read)
Fig. 25
Structure of serial I/O control register ( is internal system clock)
Clock Asynchronous Serial I/O (UART)
The UART is a full duplex asynchronous transmit/receive unit. The built-in clock divider and baud rate generator enable a broad range of transmission speeds. Please refer to Block diagram of UART.
(1) Description
The transmit and receive shift registers have a buffer (consisting of high and low order byte) each. Since the shift registers cannot be
written to or read from directly, transmit data is written to the transmit buffer and receive data is read from the receive buffer. A transmit or receive operation will be triggered by the transmit enable bit and receive enable bit of the UART control register UCON (see Structure of UART control register). The double function terminals P25/UTXD, P26/URTS and P24/URXD, P27/UCTS will be switched to serve as UART pins automatically.
26
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Baud rate selection
The baud rate of transmission and reception is determined by the setting of the prescaler and the contents of the UART baud rate generator register. It is calculated by: where p is the division ratio of
UART status register (USTS, Structure of UART status register)
The read-only UART status register consists of 7 bits (bit 0 to bit 6) which indicate the operating status of the UART function and various errors.
b = ---------------------------------16 p ( n + 1 )
the prescaler and n is the content of UART baud rate generator register. The prescalers division ration can be selected by the UART mode register (see below).
(3) Handshaking signals
When used as transmitter the UART will recognize the clear-tosend signal via P27/UCTS terminal for handshaking. When used as receiver it will issue a request-to-send signal through P26/URTS pin. Clear-to-send input When used as a transmitter (transmit enable bit set to "1"), the UART starts transmission after recognizing "L" level on P27/UCTS. After started the UART will continue to transmit regardless of the actual level of P27/UCTS or status of the transmit enable bit. Request-to-send output The UART controls the P26/URTS output according to the following conditions. Table 5: Output control conditions Condition Receive enable bit is set to "1" Reception completed during receive enable bit set to "1" Start bit (falling edge) detected Receive enable bit is set to "0" before reception started Hardware reset Receive initialization bit is set to "1" "H" "L" P26/URTS
UART mode register (UMOD, Structure of UART mode register)
The UART mode register allows to select the transmission and reception format with the following options: * * * word length: 7, 8 or 9 bits parity: none, odd or even stop bits: 1 or 2
It allows to select the prescalers division ratio as well.
UART baud rate generator (UBRG)
This 8 bit register allows to select the baud rate of the UART (see above). Set this register to the desired value before enabling reception or transmission.
UART control register (UCON, Structure of UART control register)
The UART control register consists of four control bits (bit 0 to bit 3) which allow to control reception and transmission.
data bus
UART control register
UART status register
transmit buffer (9)
transmit buffer empty interrupt request transmit buffer empty flag
1 1/8 1/32 "00" "01" "10"
UMOD2, 1 UMOD7, 6 UBRG (8) bit counter transmit shift register (9) UMOD4,3,2 transmission control circuit reception control circuit UMOD7, 6 bit counter receive shift register (9)
transmit register empty interrupt request P25/UTXD
1/256 "11"
transmit register empty flag P27/UCTS
P26/URTS
receive error interrupt request P24/URXD
receive error flags receive buffer (9) receive buffer full interrupt request receive buffer full flag data bus
Fig. 26
Block diagram of UART
27
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0
UART mode register UMOD (address 002016) Not used ("0" when read, do not write "1") clock divider selection bits b2 b1 0 0 : divided by 1 0 1 : divided by 8 1 0 : divided by 32 1 1 : divided by 256 Stop bits selection bit 0 : One stop bit 1 : Two stop bits Parity selection bit 0 : Even parity 1 : Odd parity Parity enable bit 0 : Parity disabled 1 : Parity enabled UART word length selection bits b7 b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not used
Fig. 27 7
Structure of UART mode register 0 UART control register UCON (address 002216) Transmit enable bit 0 : Transmit disabled (an ongoing transmission will be finished correctly) 1 : Transmit enabled Receive enable bit 0 : Receive disabled (an ongoing reception will be finished correctly) 1 : Receive enabled Transmission initialization bit 0 : No action 1 : Clear transmit buffer full flag and transmit shifter full flag, set the transmit status register bits and stop transmission Receive initialization bit 0 : No action 1 : Clear receive status flags and the receive enable bit Not used ("0" when read, do not write "1")
Fig. 28
Structure of UART control register
28
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 UART status register (address 002316) USTS Transmit register empty flag 0 : Register full 1 : Register empty Transmit buffer empty flag 0 : Buffer full 1 : Buffer empty Receive buffer full flag 0 : Buffer full 1 : Buffer empty Receive parity error flag 0 : No parity error detected 1 : Parity error detected Receive framing error flag 0 : No framing error detected 1 : Framing error detected Receive overrun flag 0 : No overrun detected 1 : Overrun detected Receive error sum flag 0 : No error detected 1 : Error detected Not used ("0" when read) Note: this register is read only; writing does not affect its contents.
Fig. 29
Structure of UART status register
29
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CAN MODULE
The CAN (Controller Area Network) interface of the 7630 group complies with the 2.0B specification, enabling reception and transmission of frames with either 11- or 29- bit identifier length. Refer to Fig. 31 for a block diagram of the CAN interface. The programmer's interface to the CAN module is formed by three status/control registers (Fig. 32, Fig. 33, Fig. 34), two bus timing control registers (Fig. 35 Fig. 36), several registers for acceptance filtering (Fig. 37), the transmit and receive buffer registers (Fig. 38) and one dominant level control bit (Fig. 22).
CAN Bus Timing Control
Each bit-time consists of four different segments (see Fig. 30): * Synchronization segment (SS), * Propagation time segment (PTS), * Phase buffer segment 1 (PBS1) and * Phase buffer segment 2 (PBS2).
Bit-time SS PTS PBS1 PBS2
Baud Rate Selection
A programmable clock prescaler is used to derive the CAN module's basic clock from the internal system clock frequency (). Bit 0 to bit 3 of the CAN bus timing control register represent the prescaler allowing a division ratio from 1 to 1/16 to be selected. So the CAN module basic clock frequency fCANB can be calculated as follows:
Sample point
Fig. 30
Bit time of CAN module
fCANB = ----------p+1
where p is the value of the prescaler (selectable from 1 to 15). The effective baud rate of the CAN bus communication depends on the CAN bus timing control parameters and will be explained below.
The first of these segments is of fixed length (one Time Quantum) and the latter three can be programmed to be 1 to 8 Time Quanta by the CAN bus timing control register 1 and 2 (see Fig. 35 and Fig. 36). The whole bit-time has to consist of minimum 8 and maximum 25 Time Quanta. The duration of one Time Quantum is the cycle time of fCANB. For example, assuming = 5 MHz, p = 0, one Time Quantum will be 200 ns long. This allows the maximum transmission rate of 625 kb/s to be reached (assuming 8 Time Quanta per bit-time).
data bus
polarity control register
CAN status/control registers
bus timing control register
acceptance mask register
acceptance code register
receive buffer 1 P31/CTX P32/CRX protocol controller transmit buffer wake-up logic CAN wake-up acceptance filter receive buffer 2
data bus
Fig. 31
Block diagram of CAN module
30
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 CAN transmit control register (address 003016) CTRM Sleep control bit 0 : CAN module in normal mode 1 : CAN module in sleep mode
Reset/configuration control bit 0 : CAN module in normal mode 1 : CAN module in configuration mode (plus reset at write)
Port double function control bit 0 : P31/CTX serves as I/O port 1 : P31/CTX serves as CTX output port
Transmit request bit 0 : No transmission requested 1 : Transmission requested (write "0" has no effect) Not used (no operation, "0" when read)
Transmit buffer control bit 0 : CPU access possible 1 : No CPU access (write "0" has no effect, while CTRM(3) = 1) Not used (no operation, "0" when read)
Transmit status bit (read only) 0 : CAN module idle or receiving 1 : CAN module transmitting
Fig. 32
Structure of CAN transmit control register
31
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 CAN receive control register (address 003D16) CREC Receive buffer control bit 0 : Receive buffer empty 1 : Receive buffer full (write "1" has no effect) Receive status bit (read only) 0 : CAN module idle or transmitting 1 : CAN module receiving Not used (do not write "1", read as "0") Auto-receive disable bit 0 : Auto-receive enabled 1 : Auto-receive disabled
Note: Suppresses reception of self initiated/transmitted frames
Not used (do not write "1", "0" when read) Fig. 33 7 Structure of CAN receive control register 0 CAN transmit abort register (address 003E16) CABORT Transmit Abort control bit 0 : No Transmit Abort Request 1 : Transmit Abort Request (write "1" has no effect, while CTRM(3) = 0)
Not used (No operation, "0" when read)
Fig. 34
Structure of CAN transmit abort register
32
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 CAN bus timing control register 1 (address 003116) CBTCON1 Prescaler division ratio selection bits
b3 b2 b1 b0
0 0 0 0: divided by 1 0 0 0 1: divided by 2 0 0 1 0: divided by 3 ... 1 1 1 0: divided by 15 1 1 1 1: divided by 16
Sampling control bit 0 : One sample per bit 1 : Three sample per bit Propagation time duration control bits
b7 b6 b5
0 0 0: One Time Quantum 0 0 1: Two Time Quanta ... 1 1 0: Seven Time Quanta 1 1 1 : Eight Time Quanta Fig. 35 7 Structure of CAN bus timing control register 1 0 CAN bus timing control register 2 (address 003216) CBTCON2 Phase buffer segment 1 duration control bits
b2 b1 b0
0 0 0: One Time Quantum 0 0 1: Two Time Quanta ... 1 1 0: Seven Time Quanta 1 1 1 : Eight Time Quanta Phase buffer segment 2 duration control bits
b5 b4 b3
0 0 0: One Time Quantum 0 0 1: Two Time Quanta ... 1 1 0: Seven Time Quanta 1 1 1 : Eight Time Quanta Synchronization jump width control bits
b7 b6
0 0 1 1 Fig. 36
0: 1: 0: 1:
One Time Quantum Two Time Quanta Three Time Quanta Four Time Quanta
Structure of CAN bus timing control register 2
33
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Acceptance code registers:
name 7 CAC0 Not used Not used Not used CSID10 CAC1 CSID5 CSID4 CSID3 CSID2
CSID9 CSID1
CSID8 CSID0 CEID16 CEID8 CEID0
CSID7
0 CSID6
address 003316 003416 003516 003616 003716
Not used Not used CEID15 CEID7 CEID14 CEID6
CAC2 Not used Not used Not used Not used CEID 17 CAC3 CAC4 CEID13 CEID5 CEID12 CEID4 CEID11 CEID3 CEID10 CEID2 CEID9 CEID1
Not used Not used
Select the bit pattern of identifiers which allows to pass acceptance filtering. 7 CAM0 Not used Not used Not used MSID 10 CAM1 MSID5 MSID4 MSID3 MSID2 0 MSID6
Acceptance mask registers:
MSID9 MSID1
MSID8 MSID0 MEID16 MEID8 MEID0
MSID7
003816 003916 003A16 003B16 003C16
Not used Not used MEID15 MEID7 MEID14 MEID6
CAM2 Not used Not used Not used Not used MEID17 CAM3 CAM4 MEID13 MEID5 MEID12 MEID4 MEID11 MEID3 MEID10 MEID2 MEID9 MEID1
Not used Not used
0 : Mask identifier bit (do not care) 1 : Compare identifier bit with acceptance code register bit (Not used: write to "0") Fig. 37 Structure of CAN mask and code registers
name CTB0, CRB0 CTB1, CRB1 CTB2, CRB2 CTB3, CRB3 CTB4, CRB4 CTB5, CRB5 CTB6, CRB6 CTB7, CRB7 CTB8, CRB8 CTB9, CRB9 CTBA, CRBA CTBB, CRBB CTBC, CRBC CTBD, CRBD
7 Not used Not used Not used SID5 SID4 SID3
0 SID10 SID2 SID9 SID1 EID17 EID9 EID1 DLC3 SID8 SID0 EID16 EID8 EID0 DLC2 SID7
RTR/SRR
offset 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16
SID6 IDE EID14 EID6 r1 DLC0
Not used Not used Not used Not used EID13 EID5 EID12 EID4 EID11 EID3 EID10 EID2 r0
EID15 EID7 RTR DLC1
Not used Not used Not used
data byte 0 data byte 1 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 Calculate the actual address as follows: TxD buffer address = 004016 + offset RxD buffer address = 005016 +offset (Not used: write to "0")
Fig. 38 Note 1:
Structure of CAN transmission and reception buffer registers All CAN related SFRs must not be written in "CAN sleep" mode.
34
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter uses the successive approximation method with 8 bit resolution. The functional blocks of the A-D converter are described below. Refer to Block diagram of A-D converter.
Channel Selector
The channel selector selects one of ports P00/AN0 to P07/AN7, and inputs its voltage to the comparator.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltage.
A-D conversion register AD
The A-D conversion register is a read-only register that stores the result of an A-D conversion. This register must not be read during an A-D conversion.
Data bus
b7 A-D control register 3
b0
A-D control circuit P00/AN0
channel selector Comparator
A-D interrupt request
A-D conversion register
P07/AN7
comparison voltage generator
VREF/Input switch bit
VREF
AVSS
Fig. 39
Block diagram of A-D converter D conversion, and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion. Bit 4 is the VREF/ Input switch bit.
A-D control register (Structure of A-D control register)
The A-D control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains "0" during an A-
35
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
0 A-D control register (address 001516) ADCON Analog input pin selection bits
b2 b1 b0
000 001 010 011 100 101 110 111
: : : : : : : :
P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7
A-D conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF/Input switch bit 0 : Off 1 : On Not used ("0" when read, do not write "1") Fig. 40 Structure of A-D control register rupt request bit to "1". The result of A-D conversion can be obtained from the A-D conversion register, AD (address 001416). Note that the comparator is linked to a capacitor, so set f(XIN) to 500 kHz or higher during A-D conversion.
A-D Converter Operation
The comparator and control circuit reference an analog input voltage with the reference voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the A-D conversion completion bit and the A-D inter-
36
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer consists of two separate counters: one 7-bit counter (WDH) and one 4-bit counter (WDL). Cascading both counters or using the high-order counter allows only to select the time-out from either 524288 or 32768 cycles of the internal clock . Refer to Fig. 41 and Fig. 42. Both counters are addressed by the same watchdog timer register (WDT). When writing to this register, both counters will be set to the following default values: * the high-order counter will be set to address 7F16 * the low-order counter will be set to address F16 regardless of the data written to the WDT register. Reading the watchdog timer register will return the corresponding control bit status, not the counter contents.
1/256
Once the WDT register is written to, the watchdog timer starts counting down and the watchdog timer interrupt is enabled. Once it is running, the watchdog timer cannot be disabled or stopped except by reset. On a watchdog timer underflow, a non-maskable watchdog timer interrupt will be requested. To prevent the system being stopped by STP instruction, this instruction can be disabled by the STP instruction disable bit of WDT register. Once the STP instruction is disabled, it cannot be enabled again except by RESET.
"1" WDL counter (4) "0" WDT7 "F16" WDH counter (7) "7F16" WDT interrupt
WDT register (8)
Fig. 41 7
Block diagram of watchdog timer 0 Watchdog timer register (address 002E16) WDT Not used (undefined when read) Stop instruction disable bit 0 : Stop instruction enabled 1 : Execute two NOP instructions instead (once this bit is set to "1" it can not be cleared to "0" again, except on RESET.) Upper byte count source selection bit 0 : Underflow of the low order counter 1 : divided by 256
Fig. 42
Structure of watchdog timer register ( is internal clock system)
37
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
The 7630 group is reset according to the sequence shown in Fig. 44. It starts program execution from the address formed by the contents of the addresses FFFB16 and FFFA16, when the RESET pin is held at "L" level for more than 2 s while the power supply voltage is in the recommended operating condition and then returned to "H" level. Refer to Fig. 43 for an example of the reset circuit.
power on power source voltage 0V reset input voltage 0V 0.8V 4.0V
VCC 1 5 M51953AL 4 0.1F RESET
3
VSS 7630 group
Fig. 43
Example of reset circuit
XIN
RESET
internal reset
Address Data
? ?
? ?
? ?
? ?
? ?
FFFA16 ADL
FFFB16
ADL, ADH
...
ADH
1st op code
8192 cycles of XIN (T1, T2)
28 to 34 cycles of XIN
24 cycles of XIN
20 cycles of XIN
Fig. 44
Reset sequence
38
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Register CPU mode reg. Interrupt request reg. A Interrupt request reg. B Interrupt request reg. C Interrupt control reg. A Interrupt control reg. B Interrupt control reg. C Port P0 reg. Port P0 direction reg. Port P1 reg. Port P1 direction reg. Port P2 reg. Port P2 direction reg. Port P3 reg. Port P3 direction reg. Port P4 reg. Port P4 direction reg. Serial I/O control reg. A-D control reg. Timer 1 Timer 2 Timer 3 Timer 123 mode reg. Timer XL
Address 000016 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001316 001516 001616 001716 001816 001916 001A16
Register contents 4816 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0816 FF16 0116 FF16 4016 FF16
Register Timer XH Timer YL Timer YH Timer X mode reg. Timer Y mode reg. UART mode reg. UART control reg. UART status reg. Port P0 pull-up control reg. Port P1 pull-up control reg. Port P2 pull-up control reg. Port P3 pull-up control reg. Port P4 pull-up/down control reg. Interrupt polarity selection reg. Watchdog timer reg. Polarity control reg. CAN transmit control reg. CAN bus timing control reg. 1 CAN bus timing control reg. 2 CAN receive control reg. CAN transmit abort reg. Processor status reg. Program counter (high-order byte) Program counter (low-order byte)
Address 001B16 001C16 001D16 001E16 001F16 002016 002216 002316 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003D16 003E16 (PS) (PCH) (PCL)
Register contents FF16 FF16 FF16 0016 0016 0010 0016 0710 0016 0016 0016 0016 0016 0016 3F16 0016 0216 0016 0016 0016 0016 0416 contents of FFFB16 contents of FFFA16
Note: The contents of RAM and registers other than the above registers are undefined after reset; thus software initialization is required. Fig. 45 Internal status of microcomputer after reset
39
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7630 group is equipped with an internal clock generating circuit. Please refer to Fig. 46 for a circuit example using a ceramic resonator or quartz crystal oscillator. For the capacitor values, refer to the manufacturers recommended parameters which depend on each oscillators characteristics. When using an external clock, input it to the XIN pin and leave XOUT open.
XIN
XOUT
CIN
COUT
Fig. 46
Ceramic resonator circuit
.
Oscillation Control
The 7630 group has two low power modes: the stop and the wait mode. Stop mode The microcomputer enters the stop mode by executing the STP instruction. The oscillator stops with the internal clock at "H" level. Timers 1 and 2 will be cascaded and initialized by their reload latches contents. The count source for timer 1 will be set to f(XIN)/16. Oscillation is restarted if an external interrupt is accepted or at reset. When using an external interrupt, the internal clock remains at "H" level until timer 2 underflows allowing a time-out until the
clock oscillation becomes stable. When using reset, a fixed time-out will be generated allowing oscillation to stabilize. Wait mode The microcomputer enters the wait mode by executing the WIT instruction. The internal clock o stops at "H" level while the oscillator keeps running. Recovery from wait mode can be done in the same way as from stop mode. However, the time-out period mentioned above is not required to return from wait-mode, thus no such time-out mechanism has been implemented. Note: Set the interrupt enable bit of the interrupt source to be used to return from stop or wait mode to "1" before executing STP or WIT instruction.
XOUT
1/4 "1"
XIN
1/2
"0" CPUM6
interrupt request interrupt disable flag RESET STP delay
R S R Q STP S
Q
D T
Q
internal clock for peripherals
2
R STP oscillator countdown (timer 1 and 2) WIT S R S
Q
D T
Q
internal clock for CPU
Q
P2
Fig. 47
Block diagram of clock generating circuit
40
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1 2 3 Mask ROM Order Confirmation Form Mark Specification Form Contents of Mask ROM, in EPROM form (three identical copies) Programming with PROM programmer The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Fig. 48 is recommended to verify programming.
PROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter. Set the address of PROM programmer to the user ROM area. For the programming adapter type name, please refer to the following table: Table 6: Programming adapter name MCU type One Time PROM EPROM Package 44P6N-A 80D0 Programming adapter type PCA7430 PCA7431 Note on screening: The screening temperature is far higher than the storage temperature. Never subject the device to 150 C exceeding 100 hours. Fig. 48 Programming and testing of One Time PROM version Functional test in target unit Verification with PROM programmer Screening *(Note) (150 C for 40 hours)
41
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7: ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Output voltage VO Pd Topr Tstg Power dissipation Operating temperature Storage temperature Power source voltage Input voltage P00--P07, P11--P17, P20--P27, P30--P34, P40--P47, RESET, XIN P00--P07, P12--P17, P20--P27, P30--P34, P40--P47, XOUT Parameter Conditions Ratings -0.3 to 7.0 -0.3 to VCC + 0.3 Unit V V
All voltages with respect to VSS and output transistors are "off".
-0.3 to VCC + 0.3 Ta = 25 C 500 -40 to 85 -60 to 150
V mW C C
Table 8: RECOMMENDED OPERATING CONDITIONS
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = - 40 to 85 C unless otherwise noted)
Limits Symbol VCC VSS VIH VIL Parameter min. Power source voltage "H" Input voltage "L" Input voltage "H" sum peak output current "H" sum average output current "L" sum peak output current "L" sum average output current "H" peak output current "H" average output current "L" peak output current "L" average output current input current at overvoltage condiP11--P17, P20--P27, tion P30--P34, P40--P47 (VI > VCC) total input current at overvoltage condition (VI > VCC) Timer input frequency
(based on 50 % duty)
Unit typ. 5.0 0 max. 5.5 V V VCC 0.2 * VCC -80 -40 80 40 -10 -5 10 5 1 V V mA mA mA mA mA mA mA mA mA 4.0
P00--P07, P11--P17, P20--P27, P30--P34, P40--P47, RESET, XIN P00--P07, P11--P17, P20--P27, P30--P34, P40--P47, RESET, XIN P00--P07, P12--P17, P20--P27, P30--P34, P40--P47
0.8 * VCC 0
IOH (peak) IOH (avg) IOL (peak) IOL (avg)
IOH (peak) IOH (avg) IOL (peak) IOL (avg) IIO
IIO
f(CNTR)
P11--P17, P20--P27, P30--P34, P40--P47 P14/CNTR0, P15/CNTR1 (except bi-phase counter mode) P13/TX0, P14/CNTR0 (bi-phase counter mode)
16
mA
f(XIN)/16 f(XIN)/32 10
MHz MHz MHz
f(XIN)
Clock input oscillation frequency
42
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9: ELECTRICAL CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = - 40 to 85 C unless otherwise noted)
Limits Symbol Parameter Test conditions min. P00--P07, P12--P17, P20--P27, P30--P34, P40--P47 P00--P07, P12--P17, P20--P27, P30--P34, P40--P47 P11/INT0, P12/INT1, P13/TX0, P14/CNTR0, P15/CNTR1,P20/SIN, P22/SCLK, P26/URTS, P27/UCTS, P32/CRX, RESET P00--P07, P11--P17, P20--P27, P30--P34, P40--P47, RESET XIN P00--P07, P11--P17, P20--P27, P30--P34, P40--P47, RESET XIN P32, P40--P47 P00--P07, P11--P17, P20--P27, P30--P34, P40--P47, RESET typ. max. Unit
VOH
"H" output voltage
IOH = -5 mA
0.8 * VCC
V
VOL
"L" output voltage
IOL = 5 mA
2.0
V
VT+ - VT-
Hysteresis
0.5
V
IIH
"H" input current
VI = VCC
5
A A A A
IIH
"H" input current
VI = VCC
4
IIL
"L" input current
VI = VSS
-5
IIL IIH
"L" input current "H" input current
VI = VSS VI = VCC Pull-Down = 'On' VI = VSS Pull-Up = 'On' When clock stopped 20
-4 200
A
IIL
"L" input current
-200
-20
A
VRAM
RAM hold voltage
2.0
V
43
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Limits Symbol Parameter Test conditions min.
high speed mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module running, ADC running high speed mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module stopped, ADC running middle speed mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module running, ADC running middle speed mode, wait mode, f(XIN) = 8MHz, VCC = 5V, output transistors off, CAN module stopped, ADC stopped stop mode, f(XIN) = 0MHz, VCC = 5V, Ta = 25C stop mode, f(XIN) = 0MHz, VCC = 5V, Ta = 85C
Unit typ. max.
11.0
18.0
mA
9.0
16.0
mA
ICC
Power source current
6.0
11.0
mA
2.0
mA
0.1
1.0 10.0
A A
Table 10: A-D converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V,
Ta = -40 to 85 C,
unless otherwise noted)
Limits Symbol -- -- tCONV VREF IREF RLADDER IIAN Resolution Absolute accuracy Conversion time Reference input voltage Reference input current Ladder resistor value Analog input current VI = VSS to VCC VCC = VREF = 5.12 V
high-speed mode middle-speed mode
Parameter
Test conditions min. typ. 1.0 106 424 2.0 150 35 0.5 5.0 max. 8 2.5 108 432 VCC 200
Unit Bit LSB tC(XIN) tC(XIN) V A k A
44
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11: Timing requirements
(VCC=4.0 to 5.5 V, VSS=AVSS=0 V, Ta=-40 to 85 C unless otherwise noted)
Limits Symbol Parameter min. tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time (except bi-phase counter mode) CNTR0 input cycle time (bi-phase counter mode) CNTR0, CNTR1 input "H" pulse width (except bi-phase counter mode) CNTR0 input "H" pulse width (bi-phase counter mode) CNTR0, CNTR1 input "L" pulse width (except bi-phase counter mode) CNTR0 input "L" pulse width (bi-phase counter mode) tL(CNTR0-TX0) tC(TX0) tWH(TX0) tWL(TX0) tWH(INT) tWL(INT) tC(SCLK) tWH(SCLK) tWL(SCLK) tSU(SIN-SCLK) tH(SCLK-SIN) Lag of CNTR0 and TX0 input edges (bi-phase counter mode) TX0 input cycle time (bi-phase counter mode) TX0 input "H" pulse width (bi-phase counter mode) TX0 input "L" pulse width (bi-phase counter mode) INT0, INT1 input "H" pulse width INT0, INT1 input "L" pulse width Serial I/O clock input cycle time Serial I/O clock input "H" pulse width Serial I/O clock input "L" pulse width Serial I/O input setup time Serial I/O input hold time 2 100 37 37 1600 2000 800 1000 800 1000 500 3200 1600 1600 460 460 8 * tC(XIN) 4 * tC(XIN) 4 * tC(XIN) 200 150 typ. max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
45
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12: Switching characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = -40 to 85 C, unless otherwise noted)
Limits Symbol Parameter min. tWH(SCLK) tWL(SCLK) tD(SCLK-SOUT) tV(SCLK-SOUT) tR(SCLK) tR(CMOS) tF(CMOS) Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rise time CMOS output rise time CMOS output fall time 10 10 0 0.5 * tC(SCLK) - 50 0.5 * tC(SCLK) - 50 50 50 50 50 50 typ. max. ns ns ns ns ns ns ns Unit
measurement output pin
100 pF
CMOS output
Fig. 49
Circuit for measuring output switching characteristics
46
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tC(TX0) tWH(TX0) TX0
0.8*VCC 0.2*VCC
tWL(TX0)
tC(CNTR) tWH(CNTR) CNTR0, CNTR1
0.8*VCC 0.2*VCC
tWL(CNTR)
tWH(INT) INT0, INT1
0.8*VCC 0.2*VCC
tWL(INT)
tWL(RESET) RESET
0.2*VCC
tC(XIN) tWH(XIN) XIN
0.8*VCC 0.2*VCC
tWL(XIN)
tC(SCLK) tF SCLK tWL(SCLK) tR
0.8*VCC 0.2*VCC
tWH(SCLK)
tSU(SIN-SCLK) SIN
0.8*VCC 0.2*VCC
tH(SCLK-SIN)
tD(SCLK-SOUT) SOUT
tV(SCLK-SOUT)
Fig. 50
Timing diagram
47
REVISION
7630 English Data Sheets
REVISION
DATE
Page
New Old
MODIFICATIONS
1.1
10. 98 11 18 26 38 41 11 18 26 38
"CAN controller" is replaced by "CAN module" in whole document. Schematics (8) and (11) are corrected. Replaced: "PUPDj" with "PUP4j" Replaced: "UTXD" with "SOUT" Replaced: "URXD" with "SIN" Replaced: "FFFBH" with "FFFB16" Replaced: "FFFAH" with "FFFA16" Replaced: "44P6N" with "44P6N-A) 43 10 35 Values changed:Iih(35, 113) to (20, 200) and Iil(-122, -70) to (-200, -20); typical values are removed. Schematic (1) is modified. Fig. 39 is modified.
(1.2)
13.01.99
43 10 35
Revision Report M37630 E4/M4
1

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